FPGA逻辑设计工作内容

1、熟悉ISE/Vivido、SDK开发环境； 2、熟练使用VHDL/VerilogHDL开发语言； 3、具备RapidIO、LVDS等高速接口设计与实现能力； 4、具备常用AD/DA配置、数字混频、FIR滤波设计与实现能力； 5、熟悉xilinx Znyq处理器系统开发， 6、硕士研究生及以上学历。

【岗位需求】 1）根据项目需求完成 FPGA 方案设计论证，完成整体架构及各子模块接口方案设计； 2）根据时序分析和资源报告，完成时序约束及资源优化等； 3）独立承担 FPGA 的逻辑设计与实现，包括各种接口、信号处理算法的设计与实现； 4）配合硬件人员完成 FPCA 部分原理图设计审核，完成 PPGA 系统验证及调试。 【任职资格】 1）本科及以上学历，具有2年及以上的FPGA 或者 ASIC 工作经验(无线通信设计优先）; 2）熟练掌握 Verilog/VHDL 语言，熟练使用 ALTERA 或者 XILINX 综合时序分析工具; 3） 能够单独阅读 MATALB 算法代码并进行 RIL代码设计、仿真验证； 4） 具有良好的沟通能力，团队协作能力，对待事情认真负责专注。 周末双休，早8:40-晚17：30

FPGA Logic Design Engineer We are looking for candidate who has an experience in Hardware/Software applications development is interested in defining, design, develop and maintain Hardware/Software based solutions for our FPGA based emulation products. Looking for someone who is excited about the daily technical and human challenges, self-motivated, pro-active, responsive, persistent, exceptional in problem solving. The Role: The candidate will be responsible for:Definition, development, validation, and deployment of HW based solutions for our emulation/Prototype platforms in multiple vertical markets. Maintain a close interaction with customers, field support, R&D, Marketing, and Sales teams in supporting HW solutions with ZeBu/HAPS platforms. Alpha/beta customer roll out and support of HW based solutions to our worldwide customers. Requirements BS/MS/PhD in Electrical, Electronic, Computer Engineering or Science, or related areas 6+ years’ relevant logic design and development experience in ASIC/FPGA designs targeted for full SOC applications. Work related experience on two or more protocols like Ethernet, PCI Express, SATA, SAS, USB an essential requirement. Strong RTL design background with Xilinx FPGA implementation direct experience with minimum 5 years of coding and Xilinx FPGA implementation. Good understanding of RTL, testbench, synthesis, mapping RTL to Xilinx FPGA based platform, Unix/Linux development environment.Good understanding of synthesis and timing analysis concepts Excellent knowledge on FPGA prototyping is essential.Experience in development/validation of HW/SW Emulation solutions is a plus. Experience with Xilinx transceivers is a big plus. Excellent knowledge on programming languages C/C++/ System Verilog/Verilog/Perl/Python/TC is a plus. Experience on Advanced functional SoC verification, UVM is a plus.Excellent communication skills are required.

We are looking for candidate who has an experience in Hardware/Software applications development is interested in defining, design, develop and maintain Hardware/Software based solutions for our FPGA based emulation products. Looking for someone who is excited about the daily technical and human challenges, self-motivated, pro-active, responsive, persistent, exceptional in problem solving. The Role: The candidate will be responsible for: Definition, development, validation, and deployment of HW based solutions for our emulation/Prototype platforms in multiple vertical markets. Maintain a close interaction with customers, field support, R&D, Marketing, and Sales teams in supporting HW solutions with ZeBu/HAPS platforms. Alpha/beta customer rollout and support of HW based solutions to our worldwide customers. Requirements BS/MS/PhD in Electrical, Electronic, Computer Engineering or Science, or related areas 6+ years’ relevant logic design and development experience in ASIC/FPGA designs targeted for full SOC applications. Work related experience on two or more protocols like Ethernet, PCI Express, SATA, SAS, USB an essential requirement. Strong RTL design background with Xilinx FPGA implementation direct experience with minimum 5 years of coding and Xilinx FPGA implementation. Good understanding of RTL, testbench, synthesis, mapping RTL to Xilinx FPGA based platform, Unix/Linux development environment. Good understanding of synthesis and timing analysis concepts Excellent knowledge on FPGA prototyping is essential. Experience in development/validation of HW/SW Emulation solutions is a plus. Experience with Xilinx transceivers is a big plus. Excellent knowledge on programming languages C/C++/ System Verilog/Verilog/Perl/Python/TC is a plus. Experience on Advanced functional SoC verification, UVM is a plus. Excellent communication skills are required.

岗位职责： 1. 参与ASIC/FPGA功能模块的方案设计。 2. 负责相应模块的RTL编码实现。 3. 协同验证团队进行单元验证和集成验证。 4. 负责相应模块的逻辑综合、时序收敛、设计优化、上板调试。 5. 负责相应模块的设计文档和用户手册的撰写以及维护。 任职要求： 1. 电子、计算机或相关技术专业本科及以上学历，一本或985、211优先 2. 熟悉Verilog RTL 编码、跨时钟域处理、逻辑综合约束、时序收敛等基本技能 3. 熟悉Ethernet, IP, TCP / UDP协议, 有Switch / Router产品设计经验者优先 4. 熟悉OVS、VIRTIO、SR-IOV、DPDK / SPDK、P4，有智能网卡产品设计经验者优先 5. 熟悉ARM/RISC-V，SoC集成，有SerDes、PCIE、AXI、DDR等IP的应用经验者优先 6. 熟悉 VCS, Design Compiler, Spyglass, PrimeTime 等ASIC设计软件（ASIC） 7. 具有成功流片经验（ASIC）优先

年底1-2个月的年终奖

岗位职责： 1、负责FPGA代码编写、模块设计及仿真； 2、配合软、硬件设计人员完成相关设计、调试任务； 3、完成方案文档、项目文档、质量记录及相关文档； 4、协助测试工程师制定测试计划，完成问题复现。 任职要求： 1、通信、计算机、电子等专业本科以上学历， 5年以上工作经验； 2、精通Verilog/VHDL语言；有至少3年以上Altera/Xilinx系列FPGA芯片开发经验，熟悉使用仿真，综合实现和时序分析; 熟悉FPGA调试工具； 3、熟悉 USB、PCIE、以太网、DDR、LVDS、AXI等常用接口协议的优先考虑； 4、熟悉使用UVM/SystemVerilog的优先考虑； 5、熟悉使用脚本语言，如tcl, perl, python； 6、具有良好的英文沟通能力及阅读能力。

工作地点：上海/南京 工作职责： 1. 按照项目要求负责各类装备的下位机程序开发与交付，包括FPGA逻辑设计，嵌入式程序设计； 2. 负责系统/模块的方案设计，算法设计等； 3. 负责代码编写，仿真，资源与时序优化，调试等工作； 4. 配合软、硬件设计人员完成相关任务目标； 5. 制定项目计划，与相关团队沟通合作，确保按时高质量的交付。 任职资格： 1. 本科及以上学历，三年以上相关的工作经验； 2. 熟练掌握VHDL/Verilog/C语言的开发编程，具有良好的编码风格，良好的仿真验证能力和时序分析能力； 3. 熟练使用ISE、Vivado、Quartus 、ModelSim、ChipScope、Keil等设计软件和调试工具； 4. 熟悉xilinx或altera厂家的FPGA芯片结构，熟悉STM32的应用，使用过xilinx zynq器件者优先； 5. 熟悉UART/I2C/I2S/SPI/USB/MIPI/PCIE/memory等接口协议； 6. 熟悉示波器等测试仪器的使用； 7. 具备较强的分析解决问题能力、良好的学习和文档撰写能力； 8. 良好的沟通能力，团队合作精神，积极主动，有责任心。

处理器前端逻辑设计，要求熟悉计算机体系结构，arm架构规范，arm amba协议族(axi5和chi)，精通数字电路设计，Verilog语言，理解综合和SDC，熟练操作相关EDA工具。 北京天津均有岗位。

处理器前端逻辑设计，要求熟悉计算机体系结构，arm amba协议族，数字电路设计，Verilog语言，理解综合和SDC，熟练操作相关EDA工具。