高级测试工程师

Job Purpose To contribute to NPI to achieve overall business goals, contribute to QFD, NPI Design / Technical Review at development stage. Ensure new products are designed according to design rules, process capability and manufacturability (target DFM & 6 sigma). Duties and Responsibilities • Responsible to secure POR to meet back-end manufacturing KPI requirements(Quality, Cost/Yield, Cycle Time). o Responsible for robust test solution development with early design review involvement to meet design for test requirement. o Initiate to review test coverage & guard band with previous lesson learns to secure new device performance in both Quality and Yield. o Establish auto pre-alert on “suspecting” wafers with FAB critical EWB TAS setup for KGD early detection. o To capture all potential failure mode via EON sample build characterization and reflect to DFMEA RPN. Close loop activities to reduce RPN to acceptable level with systematic solution of controllable KPIVs to minimize post code S changes. o To provide on schedule APQP test deliverables to meet marketing release time. o Initiate test maverick criteria and process control specs/WI for post code S. • Responsible for new released device post code S management during ramp up until it meet criteria to hand over to sustaining process engineering o Responsible for yield improvement & quality enhancement to stabilize device performance at post code S ramp up. o Maverick limit adjustment and initiate PAT limit for new production to capture all excursed units. o Contribute to mass production cycle time improvement with test time reduction and MTBA improvement to meet on time delivery requirement. o Failure mode pareto and electrical reading drifting comparison between NPI and Post Code S for proactive risk assessment with early prevention. o Responsible for RMP failure analysis with improvement plan, define specific RMP plan for device reliability monitoring to detect any potential quality risks prior to customer field application fail. • Leadship to address related Assy/FAB process owner for improvement on key FT failure items. • Establish robust test coverage in final test area, familiar with assembly failure modes captured into characterization of test sensitivity and screenability • Statistic analysis on electrical characterization & reliability drifting • Sufficient & Robust risk assessment during Design review. • Align with Test platform/solution roadmap for new test solution development or setup. Qualifications • 6+ years’ product or test engineering experience of semiconductor device such as power discrete (BJT, MOSFET, IGBT, Diode), multi-chip functional power module, analog switch, PWM, power conversion IC, etc. • Knowledge of key power discrete and Module package and key assembly process • Understand Failure analysis on Major FT failure items • Know key failures which critical to customer application, know product major application • Understand product reliability items and application with failure mode of device • Familiar with C/C++ language programming • Good English communication skills including verbal and written • Familiar with data statistics tooling such as JMP • Team player with good interpersonal skills and able to work efficiently with multi-functional groups across different department and location. • Proactive, self-motivated, result/goal oriented and be willing to face pressure and challenge. • Bachelor degree or equivalent in EE, Micro-electronics, Automatic Control or relative specialty.